Advanced Packaging Workshop

SEMI Southeast Asia

Interaction of Substrate and PCB to Microelectronics Packaging Assembly and Reliability

Malaysian International Trade & Exhibition Centre (MITEC)

Substrate and PCB technologies are the building blocks for Microelectronics Packaging and surface mount packages. This course will coverSubstrate and PCB fabrication processes and its key process and materials such as ABF,BT,FR5 etcBuild-up micro-via technologies with use of lasers, plasma, photo materials etc. Registration and tolerances of substrate design in relation to substrate and PCB fabrication process which includes via to pattern, pattern to resist etc, which can affect microelectronics assembly processesMaterials, design and surface finishes (Cu, NiAu, ENIG, NiPdAu etc) with respect to assembly processes and parameters. Substrate defects and package reliability including failure of fatigue, kirkendall voids and intermetallics <h1>About the trainer</h1>Dr Lee Teck Kheng received the B.S. degree in mechanical engineering and the M.S. degree in materials science and engineering from the National University of Singapore in 1995 and 1999, respectively and the Ph.D. degree in Mechanical and Aerospace Engineering from the Nanyang Technology University, Singapore, in 2006. Dr Lee founded Technology Development Centre at ITE College Central. He drives ITE innovations through development of strategic plans and organization re-structure. The ITE Technology Transfer office was setup in 2018 and collaborated with various Institute of higher IEOs to catalyze Singapore Research Innovation Enterprise Initiative. Dr Lee has authored and co-authored more than 60 papers in journal and international conferences. He holds 74 U.S patents, with another 20 patents pending issuance. He serves as a current/past committee member of Singapore Chinese Chamber of Commerce, SEMI and SSIA, IEEE semiconductor group, EPTC. Currently, he leads the aligning of international standard for semiconductor under IEC TC47. He taught as a part-time lecturer in NTU for Microelectronics packaging since 2009-2014. He is also a member of IEEE, CPMT, IES, Material Research Society (MRS) and IMPAS societies. He also conducted several oversea workshops as well as honor in Marquis Who’s Who (2008-2020) and International Biographical Centre.

Day 1 Agenda

Day 1: 8/3/2023 -Registration

Introduction Core Materials – FR4, BT, ABF etc. Key Processes Mechanical, laser drilling Patterning exposure, develop, etch, strip Electroless and electrolytic plating Lamination and buildup 2 Layer fabrication flow

Substrate & PCB Materials and Fabrication Flow

Lunch

Mechanical registration and tolerances Cu patterning registration and tolerances Solder registration and tolerances Substrate challenges and constraints Plating finishes Problem solving exercises on Assembly Challenges

Design and Tolerances Affecting Packaging

Q&A Discussion

End of Day 1

Day 2 Agenda

Day 2 : 9/3/2023 - Registration

Assembly differences in PCB and substrate Surface finishes for assembly Substrate surface finishes for packaging, soft Ni/Au for wirebonding, ball attach PCB surface finishes for 2nd interconnect, ENIG, NiPdAu and Cu with OSP Strip warpage Thermal stress and shrinkage affecting warpage Slots, Cu patterning and solder resist thickness impacting warpage Other assembly challenges Solder cracks, solder balling, component lifting, poor wetting, flux residue

Assembly Challenges and Defects

Interconnect reliability Intermetallic failure, interdiffusion Fatigue and creep failure

Reliability

End of Workshop

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Advanced Packaging Workshop

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Advanced Packaging Workshop

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